PLLs are well known and widely used in the electronics industry. Within the digital field, PLLs are used in a variety of applications. Such applications include, for example, frequency synthesizers, clock generation, clock recovery and the like. PLLs are typically designed to perform within a given set of boundary conditions and to perform according to a specified standard. Typical conditions include, for example, performance over operating temperature ranges, sensitivity to noise, output sensitivity to interference, and the like. Typical performance standards include, for example, output signal frequency stability, output signal programmability, and the like.
A typical prior art PLL circuit generates an oscillating output signal having a specified frequency. The frequency of the output is tunable and is a function of an input frequency, the dividers, or the like. The type of application in which the PLL circuit is used dictates its operating conditions and performance requirements.
In addition, the type of application also largely determines type of fabrication technology used to manufacture the PLL. A large number of modern digital integrated circuits are fabricated using well known and widely used CMOS technology. Where the PLL circuit is included in a CMOS IC (integrated circuit), it is usually fabricated in CMOS (e.g., fabricated using CMOS process technology).
There is a problem, however, when the application in which the overall IC is used requires the PLL circuit to have low spurs. For example, where the IC is part of a high speed serial transmission system (e.g., high speed wireless transmission systems) it is important that the output signal of the PLL circuit shows low spurs. Spurs in a PLL refers to the pulses at the output of a charge-pump of the PLL which causes a ripple at the input of the VCO, and thus modulates the VCO frequency. This will cause sidebands around the fundamental frequency of the PLL. These sidebands are generally referred to as spurs. Prior art CMOS PLLs have tried to solve this issue but in some cases the complexity of the prior art techniques make the system unreliable and in other cases with simple techniques, the performance is not that good.
Thus, what is required is a CMOS PLL circuit which solves the low spurs and low noise operation problems of the prior art. What is required is a circuit capable of reliable operation while exhibiting low spurs on the output signal. What is required is a circuit which produces a stable output signal with a waveform with low noise, free of defects and irregularities. The present invention provides an advantageous solution to the above requirements.